1. Field of the Invention
The present invention relates to a comparator structure for use in high accuracy applications such as analog to digital converters (ADC).
2. Related Art
Comparators are often used in high accuracy applications, such as analog-to-digital conversion. In these applications, quiet high and low voltage supplies are required to achieve low supply noise. However, many known comparators have large current spikes on one or both voltage supplies during output transitions. These current spikes can interfere with chip operation. For example, an image sensor chip may include many column-parallel comparators, each having an output that switches when an input ramp signal reaches a reference level. If the outputs of many comparators transition at the same time, large current spikes may exist on the VDD or ground rails, thereby creating significant noise that may adversely impact comparators having outputs that have not yet transitioned.
FIG. 1 is a circuit diagram of a conventional differential comparator 100, exhibits a large current spike when the output of the comparator changes state. Differential comparator 100 includes PMOS transistors 101-102, NMOS transistors 103-104, output capacitor 105 and current source 110. PMOS transistors 101 and 102 form a simple differential input pair, which is connected to the active a load formed by NMOS transistors 103 and 104 and capacitor 105. The gate of PMOS transistor 101 is configured to receive a ramp voltage V+, and the gate of PMOS transistor 102 is configured to receive a reference voltage V−. As the ramp voltage V+ rises from ground level to the VDD supply voltage, the supply current (I) provided by current source 110 changes in the manner described below.
When the ramp voltage V+ is less than the reference voltage V−, current flows through PMOS transistor 101, and current source 110 provides a maximum current. When the ramp voltage V+ reaches or exceeds the reference voltage V−, no current flows through PMOS transistor 101. At this time, current will flow through PMOS transistor 102 until the output voltage VOUT of the comparator increases to VDD. At this time, PMOS transistor 102 and current source 110 stop charging capacitor 105 and current flow through PMOS transistor 102 stops. Thus, the current drawn by comparator 100 transitions from a maximum current (when V+ is less than V−) to zero current (when V+ exceeds V−). Some comparators attempt to limit this current transition by connecting the gate of NMOS transistor 104 to a constant bias voltage. However, even in these comparators, the supply current transitions from a maximum current to a current equal to one half of the maximum current.
U.S. Pat. No. 5,070,259, issued to Rempfer et al., describes an amplifier stage for use in a comparator, wherein the amplifier stage draws a substantially continuous supply current for different values of input voltage. However, this amplifier stage undesirably exhibits a relatively low gain, requiring a large number of amplifier stages to be connected in series in order to provide an adequate gain. In addition, an input capacitor and an output capacitor must be connected in the signal path of the series-connected amplifier stages.
It would therefore be desirable to have a comparator that does not experience current spikes on either the VDD or ground supplies during output transitions of the comparator. It would further be desirable if such a comparator does not require an overly complicated structure, a large number of circuit elements, or capacitors connected in the signal path. It would further be desirable for such a comparator to have an input offset cancellation option.